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HD404618 series 4-bit single-chip microcomputer rev. 6.0 sept. 1998 description the HD404618 series is designed with the powerful and efficient architecture of the hmcs400 family. the mcu incorporates a high-precision dual-tone multifrequency (dtmf) circuit, lcd driver/controller, voltage comparator, and 32-khz watch oscillator circuit. the HD404618 series includes five chips: the hd404612 with 2-kword rom; the hd404614 with 4- kword rom; the hd404616 with 6-kword rom; the HD404618 with 8-kword rom; the hd4074618 with 8-kword prom. the hd4074618, incorporating prom, is a ztat ? microcomputer that can dramatically shorten system development periods and smooth the process from debugging to mass production. ztat : zero turn around time ztat is a trademark of hitachi ltd. features 2048-word 10-bit rom (hd404612) 4096-word 10-bit rom (hd404614) 6144-word 10-bit rom (hd404616) 8192-word 10-bit rom (HD404618, hd4074618) 1184-digit 4-bit ram 30 i/o pins ? 10 high-current output pins ? cmos i/o pin circuit configuration ? input/output pull-up mos can be selected by software on-chip dtmf generator lcd controller/driver (32 segments 4 commons) three timer/counters clock-synchronous 8-bit serial interface six interrupt sources ? two by external sources ? four by internal sources
HD404618 series 2 subroutine stack up to 16 levels, including interrupts instruction cycle time ? 10 m s (f osc = 400 khz) ? 5 m s (f osc = 800 khz) four low-power dissipation modes ? stop mode ? standby mode ? watch mode ? subactive mode built-in oscillator ? crystal or ceramic oscillator (an external clock also possible) voltage comparator (2 channels) two operating modes ? mcu mode ? prom mode (hd4074618) package ? 80-pin plastic flat package (fp-80b) (fp-80a) ? 80-pin plastic thin flat package (tfp-80) ordering information type product name model name rom (word) package mask rom hd404612 hd404612fs 2,048 fp-80b hd404612h fp-80a hd404612tf tfp-80 hd404614 hd404614fs 4,096 fp-80b hd404614h fp-80a hd404614tf tfp-80 hd404616 hd404616fs 6,144 fp-80b hd404616h fp-80a hd404616tf tfp-80 HD404618 HD404618fs 8,192 fp-80b HD404618h fp-80a HD404618tf tfp-80 ztat ? hd4074618 hd4074618fs 8,192 fp-80b hd4074618h fp-80a hd4074618tf tfp-80
HD404618 series 3 pin arrangement d reset osc osc v v v com4 v vt toner tonec com3 com2 com1 d 1 0 2 cc ref 3 2 1 r2 r2 r2 r3 seg2 seg3 seg4 seg5 timo/r3 int /r3 int /r3 seg1 seg6 seg7 seg8 r2 3 0 2 1 2 1 0 0 3 1 1 1 2 3 4 5 6 7 8 9 10 11 12 14 13 15 17 16 18 20 19 22 21 24 23 64 63 62 61 60 59 58 57 56 55 54 53 51 52 50 48 49 47 45 46 43 44 41 42 26 27 28 29 34 35 36 37 30 31 32 33 38 39 40 25 79 78 77 76 71 70 69 68 75 74 73 72 67 66 65 80 (top view) (top view) fp-80b seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 d d d vc /d comp 0 /d comp 1 /d x1 test x2 sck /r0 gnd si/r0 r0 so/r0 r1 r1 r1 r1 2 4 5 6 7 8 9 10 11 12 13 0 1 2 3 0 1 2 3 ref d d d d 3 d d 1 2 3 4 5 6 7 8 9 10 11 12 14 13 15 17 16 18 20 19 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 47 48 46 44 45 43 41 42 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 fp-80a tfp-80 d d d reset v v v osc v com4 com3 d 3 2 3 2 1 2 vt com2 com1 seg32 seg31 1 0 osc 1 cc ref toner tonec r2 r2 r2 r3 seg2 seg3 seg4 seg5 timo/r3 int /r3 int /r3 seg1 seg6 seg7 seg8 r2 3 0 2 1 2 1 0 0 1 seg9 seg10 r1 r1 3 3 2 d d d d d 4 5 6 7 8 9 d 10 d 11 vc /d ref comp 0 /d comp 1 /d 12 13 test x1 x2 gnd sck /r0 0 si/r0 1 so/r0 2 r0 3 r1 0 r1 1 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11
HD404618 series 4 pin description pin number pin number fp-80b fp-80a, tfp-80 pin name i/o fp-80b fp-80a, tfp-80 pin name i/o 179 d 2 i/o 33 31 seg1 o 280 d 3 i/o 34 32 seg2 o 31 d 4 i/o 35 33 seg3 o 42 d 5 i/o 36 34 seg4 o 53 d 6 i/o 37 35 seg5 o 64 d 7 i/o 38 36 seg6 o 75 d 8 i/o 39 37 seg7 o 86 d 9 i/o 40 38 seg8 o 97 d 10 i 41 39 seg9 o 10 8 d 11 /vc ref i 42 40 seg10 o 11 9 d 12 /comp 0 i 43 41 seg11 o 12 10 d 13 /comp 1 i 44 42 seg12 o 13 11 test i 45 43 seg13 o 14 12 x1 i 46 44 seg14 o 15 13 x2 o 47 45 seg15 o 16 14 gnd 48 46 seg16 o 17 15 r0 0 / sck i/o 49 47 seg17 o 18 16 r0 1 /si i/o 50 48 seg18 o 19 17 r0 2 /so i/o 51 49 seg19 o 20 18 r0 3 i/o 52 50 seg20 o 21 19 r1 0 i/o 53 51 seg21 o 22 20 r1 1 i/o 54 52 seg22 o 23 21 r1 2 i/o 55 53 seg23 o 24 22 r1 3 i/o 56 54 seg24 o 25 23 r2 0 i/o 57 55 seg25 o 26 24 r2 1 i/o 58 56 seg26 o 27 25 r2 2 i/o 59 57 seg27 o 28 26 r2 3 i/o 60 58 seg28 o 29 27 r3 0 i/o 61 59 seg29 o 30 28 r3 1 /timo i/o 62 60 seg30 o 31 29 r3 2 / int 0 i/o 63 61 seg31 o 32 30 r3 3 / int 1 i/o 64 62 seg32 o
HD404618 series 5 pin number pin number fp-80b fp-80a, tfp-80 pin name i/o fp-80b fp-80a, tfp-80 pin name i/o 65 63 com1 o 73 71 toner o 66 64 com2 o 74 72 vt ref 67 65 com3 o 75 73 v cc 68 66 com4 o 76 74 osc 1 i 69 67 v 1 77 75 osc 2 o 70 68 v 2 78 76 reset i 71 69 v 3 79 77 d 0 i/o 72 70 tonec o 80 78 d 1 i/o note: i/o: input/output pin, i: input pin, o: output pin pin functions power supply v cc : apply power voltage to this pin. gnd: connect to ground. test : used for test purposes only. connect it to v cc . reset: resets the mcu. oscillators osc 1 , osc 2 : used as pins for the internal oscillator circuit. they can be connected to a ceramic resonator, or osc 1 can be connected to an external oscillator circuit. x1, x2: used for a 32.768-khz crystal oscillator that acts as a clock. ports d 0 ? 13 (d port): input/output port addressable by individual bits. d 0 ? 9 are i/o pins and d 10 ? 13 are input pins. d 0 ? 9 are high current output pins (15 ma, max.). d 11 ? 13 are also available as voltage comparators. r0?3 (r ports): input/output ports addressable in 4-bit units. r0 0 , r0 1 , r0 2 , r3 1 , r3 2 , and r3 3 , are multiplexed with sck , si, so, timo, int 0 , and int 1 , respectively.
HD404618 series 6 interrupts int 0 , int 1 : input external interrupts to the mcu. int 1 is also used as an external event input for timer b. int 0 and int 1 are multiplexed with r3 2 and r3 3 , respectively. serial communications interface sck : input/output serial clock pin multiplexed with r0 0 . si: serial receive data input pin multiplexed with r0 1 . so: serial transmit data output pin multiplexed with r0 2 . timers timo: outputs a variable-duty square wave. it is multiplexed with r3 1 . lcd driver/controller v 1 , v 2 , v 3 : power supply pins for the lcd driver. internal resistors provide the voltage level for each pin. the voltage condition is v cc 3 v 1 3 v 2 3 v 3 3 gnd. com1?om4: common signal output pins for lcd display. seg1?eg32: segment signal output pins for lcd display. dtmf generator toner, tonec, vt ref : dtmf signal pins. toner and tonec transmit signals for row and column, respectively. vt ref is a reference voltage for dtmf signals. apply condition v cc 3 vt ref 3 gnd to vt ref . voltage comparator comp0, comp1, vc ref : comp0 and comp1 are analog inputs for the voltage comparator. vc ref is a reference voltage pin that inputs the threshold voltage of the analog input pin.
HD404618 series 7 block diagram internal address bus system control circuit ram (1,184 4 bits) w (2 bits) x (4 bits) spx (4 bits) y (4 bits) spy (4 bits) ca (1 bit) st (1 bit) a (4 bits) b (4 bits) sp (10 bits) instruction decoder pc (14 bits) rom (2,048 10 bits) (4,096 10 bits) (6,144 10 bits) (8,192 10 bits) d port alu cpu int 0 int 1 timer b timer c timo d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 12 d 11 d 13 r0 port r0 0 r0 1 r0 2 r0 3 r1 port r1 0 r1 1 r1 2 r1 3 r2 port r2 0 r2 1 r2 2 r2 3 r3 port r3 0 r3 1 r3 2 r3 3 reset test osc osc x1 x2 v cc gnd timer a external interrupt control circuit internal data bus internal data bus high current pins lcd controller/ driver circuit v 1 v 2 v 3 com1 com2 com3 com4 seg1 seg2 seg3 seg31 seg32 dtmf generation circuit vt ref toner tonec vc ref comp 0 comp 1 compa- rator serial interface si so sck : data bus : signal lines 1 2
HD404618 series 8 memory map rom memory map the rom memory map is shown in figure 1, and the rom is described below. 0 15 16 63 64 4095 4096 8191 8192 16383 0 $000f $0fff $1000 $1fff $2000 $3fff $0010 $003f $0040 vector address zero-page subroutine (64 words) pattern (4096 words) not used 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f jmpl instruction (jump to reset routine) jmpl instruction (jump to int routine) 0 jmpl instruction (jump to timer a routine) 1 jmpl instruction (jump to timer b routine) jmpl instruction (jump to timer c routine) jmpl instruction (jump to serial routine) jmpl instruction (jump to int routine) * hd404612: 2048 words hd404614: 4096 words hd404616: 6144 words HD404618, hd4074618: 8192 words program * note: figure 1 rom memory map vector address area ($0000?000f): reserved for jmpl instructions that branch to the start addresses of the reset and interrupt routines. after an mcu reset or interrupt execution, the program starts from the vector address. zero-page subroutine area ($0000?003f): reserved for subroutines. the program branches to a subroutine in this area in response to the cal instruction. pattern area ($0000?0fff): contains rom data that can be referenced with the p instruction. program area ($0000?07ff (hd404612), $0000?0fff (hd404614), $0000?17ff (hd404616), $0000?1fff (HD404618, hd4074618)): used for program coding.
HD404618 series 9 ram memory map the mcu contains a 1,184-digit 4-bit ram area consisting of a data area and a stack area. in addition, interrupt control bits and special registers are mapped onto the same ram memory space outside this area. the ram memory map is shown in figure 2, and described below. interrupt control bits area ($000?003): used for interrupt control bits and the bit register (figure 3). the register flag area consists of lson, wdon, tgsp, and dton flags. both areas can be accessed only by ram bit manipulation instructions. in addition, note that the interrupt request flag cannot be set by software, the rsp bit is used only to reset the stack pointer. limitations on using the instructions are shown in figure 4. register flag area ($020?023): consist of the lson, wdon, tgsp, and dton flags which are bit registers accessible by ram bit manipulation instructions. the wdon flag can only be set, only by the sem/semd instruction. the tgsp flag can be set and reset by the sem/semd and rem/remd instructions. the dton flag can be set, reset, and tested by the sem/semd, rem/remd, and tmd instructions. note that the dton flag is active only in subactive mode, and is normally reset in active mode. special function registers area ($004?01f, $024?03f): used as mode or data registers for serial interface, timer/counters, lcd, and dtmf, and as data control registers for i/o ports. these registers are classified into three types: write-only, read-only, and read/write as shown in figure 2. the sem/rem and semd/remd instructions can be used for the lcd control register (lcr), but ram bit manipulation instructions cannot be used for other registers. lcd data area ($050?06f): used for storing lcd data which is automatically output to lcd segments as display data. data 1 lights the corresponding lcd segment; data 0 extinguishes it. this area can be used as data area. data area ($040?2cf, $100?2cf; bank 0, 1): the memory registers (mr), which consist of 16 digits ($040?04f), can be accessed by the lamr and xmra instructions (see figure 5). in the 464 digits from $100?2cf, a bank can be selected by the v register (see section on v register). stack area ($3c0?3ff): used for saving the contents of the program counter (pc), status flag (st), and carry flag (ca) at subroutine call (cal or call instruction) and interrupt processing. this area can be used as a 16-level nesting subroutine stack in which one level requires four digits. the data to be saved and the save conditions are shown in figure 5. the program counter is restored by either the rtn or rtni instruction, but the status and carry flags can only be restored by the rtni instruction. any unused space in this area is used for data storage.
HD404618 series 10 0 $000 $000 63 64 80 112 959 960 1023 $03f $040 $050 $070 $100 $3ff 4 5 6 7 0 1 2 3 12 13 14 15 8 9 10 11 16 17 32 35 48 18 19 20 49 50 51 63 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $020 $023 $030 $031 $032 $033 $03b $03c $03d $03f $00a $00b $00e $00f w w r/w w w w w w w w w w w w w w w w w w w w r r r r w r/w r/w r/w r/w r/w r/w $100 $2cf 61 59 60 $3bf $3c0 $2cf ram-mapped registers memory registers (mr) lcd display area (32 digits) data (144 digits) data (464 digits 2) v = 0 (bank 0) v = 1 (bank 1) not used stack (64 digits) interrupt control bits area port mode register a (pmra) serial mode register (smr) serial data register lower (srl) serial data register upper (sru) timer mode register a (tma) timer mode register b (tmb) timer b (tcbl/tlrl) (tcbu/tlru) miscellaneous register (mis) timer mode register c (tmc) timer c (tccl/tcrl) (tccu/tcru) tg mode register (tgm) tg control register (tgc) port mode register b (pmrb) lcd control register (lcr) lcd mode register (lmr) not used register flag area not used port r0 dcr (dcr0) port r1 dcr (dcr1) port r2 dcr (dcr2) port r3 dcr (dcr3) not used port d ? dcr (dcrb) port d ? dcr (dcrc) port d ? dcr (dcrd) not used v register (v-reg) 03 47 89 data (464 digits) v = 0 (bank 0) data (464 digits) v = 1 (bank 1) 10 11 14 15 timer counter b, lower (tcbl) timer counter b, upper (tcbu) timer counter c, lower (tccl) timer counter c, upper (tccu) timer load register b, lower (tlrl) timer load register b, upper (tlru) timer load register c, lower (tcrl) timer load register c, upper (tcru) r: read only w: write only r/w: read/write * note: do not use any area labelled ?ot used * the data area has two banks: v = 0 (bank 0) and v = 1 (bank 1) figure 2 ram memory map
HD404618 series 11 0 1 2 3 bit 3 bit 2 bit 1 bit 0 im0 (im of int ) 0 if0 (if of int ) 0 rsp (reset sp bit) ie (interrupt enable flag) imta (im of timer a) ifta (if of timer a) im1 (im of int ) 1 if1 (if of int ) 1 imtc (im of timer c) iftc (if of timer c) imtb (im of timer b) iftb (if of timer b) not used not used ims (im of serial) ifs (if of serial) $000 $001 $002 $003 32 35 dton direct transfer on flag tgsp (tone generator speed flag) wdon (watchdog on flag) lson (low speed on flag) not used $020 $021 $023 if: interrupt request flag im: interrupt mask ie: interrupt enable flag sp: stack pointer note: bits in the interrupt control bits area and register flag area are set by the sem or semd instruction, reset by the rem or remd instruction, and tested by the tm or tmd instruction. other instructions have no effect. figure 3 configuration of interrupt control bits and register flag areas if rsp wdon tgsp dton sem/semd rem/remd tm/tmd not executed allowed allowed not executed allowed inhibited allowed not executed inhibited allowed allowed inhibited not executed in active mode allowed allowed used in subactive mode note: wdon is always reset in active mode. dton is always reset in active mode. if the tm or tmd instruction is executed for the inhibited bits or non-existing bits, the value in st becomes invalid. figure 4 usage limitations of ram bit manipulation instructions
HD404618 series 12 pc ?c : program counter st: status flag ca: carry flag 13 0 memory registers stack area 64 $040 960 $3c0 65 $041 66 $042 67 $043 68 $044 69 $045 70 $046 71 $047 72 $048 73 $049 74 $04a 75 $04b 76 $04c 77 $04d 78 $04e 79 $04f mr (0) mr (1) mr (2) mr (3) mr (4) mr (5) mr (6) mr (7) mr (8) mr (9) mr (10) mr (11) mr (12) mr (13) mr (14) mr (15) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 1023 $3ff st pc 10 pc 13 pc 12 pc 11 ca pc 3 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 2 pc 1 pc 0 bit 3 bit 2 bit 1 bit 0 $3fc $3fd $3fe $3ff 1022 1023 1020 1021 figure 5 configuration of memory registers and stack area, and stack position
HD404618 series 13 functional description registers and flags the mcu has ten registers and two flags for cpu operations. they are illustrated in figure 6 and described below. 30 30 30 30 30 30 0 0 0 13 95 1 v b a w x y spx spy ca st pc sp 11 11 accumulator b register v register w register x register y register spx register spy register carry flag status flag program counter stack pointer 0 0 0 figure 6 registers and flags accumulator (a), b register (b): four-bit registers used to hold results from the arithmetic logic unit (alu) and transfer data between memory, i/o, and other registers.
HD404618 series 14 v register (v): used for ram address expansion and selecting the bank of ram addresses $100?2cf (464 digits). thus, when accessing locations $100?2cf, specify the value of the v register (v = $0 for bank 0, v = $1 for bank 1). locations $000?0ff and $3c0?3ff can be accessed independent of the v register. the v register is located at ram address $03f. w register (w), x register (x), y register (y): two-bit (w) and four-bit (x and y) registers used for indirect ram addressing. the y register is also used for d-port addressing. spx register (spx), spy register (spy): four-bit registers used to supplement the x and y registers. carry flag (ca): one-bit flag that stores any alu overflow generated by an arithmetic operation. ca is affected by the sec, rec, rotl, and rotr instructions. during an interrupt, a carry is pushed onto the stack and popped from the stack by the rtni instruction?ut not by the rtn instruction. status flag (st): one-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the alu, or result of a bit test. st is used as a branch condition of the br, brl, cal, or call instruction. the contents of st remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the br, brl, cal, or call instruction is read, regardless of whether the instruction is executed or skipped. during an interrupt, the contents of st are pushed onto the stack and popped from the stack by the rtni instruction, but not by the rtn instruction. program counter (pc): a 14-bit counter that points to the rom address of the instruction being executed. stack pointer (sp): ten-bit pointer that contains the address of the stack area to be used next. the sp is initialized to $3ff by mcu reset, is decremented by 4 when data is pushed onto the stack, and is incremented by 4 when data is popped from the stack. since the top four bits of the sp are fixed at 1111, a stack of up to 16 levels can be used. the sp can also be initialized to $3ff in another way: by resetting the rsp bit with the rem or remd instruction.
HD404618 series 15 reset the mcu is reset by inputting a high-level voltage to the reset pin. at power-on or when stop mode is cancelled, reset must be high for at least one t rc to enable the oscillator to stabilize. during operation, reset must be high for at least two instruction cycles. i/o pins go to high-impedance at power-on. initial values after mcu reset are shown in table 1. table 1 initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 indicates program execution point from start address of rom area status flag (st) 1 enables conditional branching stack pointer (sp) $3ff stack level 0 v register (bank register) (v) 0 bank 0 (memory) interrupt flags/mask interrupt enable flag (ie) 0 inhibits all interrupts interrupt request flag (if) 0 indicates there is no interrupt request interrupt mask (im) 1 prevents (masks) interrupt request i/o port data register (pdr) all bits 1 enables output at level 1 data control register (dcr) all bits 0 turns output buffer off (to high impedance) port mode register a (pmra) 0000 refer to description of port mode register a port mode register b (pmrb) 0000 refer to description of port mode register b timer/ counters, serial interface timer mode register a (tma) 0000 refer to description of timer mode register a timer mode register b (tmb) 0000 refer to description of timer mode register b timer mode register c (tmc) 0000 refer to description of timer mode register c serial mode register (smr) 0000 refer to description of serial mode register prescaler s $000 prescaler w $00 timer counter a (tca) $00
HD404618 series 16 table 1 initial values after mcu reset (cont) item abbr. initial value contents timer/ counters, serial interface timer counter b (tcb) $00 timer counter c (tcc) $00 timer load register b (tlr) $00 timer load register c (tcr) $00 octal counter 000 lcd lcd control register (lcr) 000 refer to description of lcd control register lcd mode register (lmr) 0000 refer to description of lcd duty cycle/clock control dtmf generator tone generator control register (tgc) 000 refer to description of tone generator control register tone generator mode register (tgm) 0000 refer to description of generator mode register bit registers low speed on flag (lson) 0 refer to description of operating modes watchdog timer on flag (wdon) 0 refer to description of timer c tone generator speed flag (tgsp) 0 refer to description of dtmf generation circuit direct transfer on flag (dton) 0 refer to description of operating modes miscellaneous register (mis) 000 item abbr. status after cancellation of stop mode by mcu reset status after cancellation of all other modes by mcu reset carry flag (ca) pre-mcu-reset values are not guaranteed; values must be initialized by program pre-mcu-reset values are not guaranteed; values must be initialized by program accumulator (a) b register (b) w register (w) x/spx register (x/spx) y/spy register (y/spy) serial data register (sr) ram pre-mcu-reset (pre-stop- instruction) values are retained
HD404618 series 17 interrupts the mcu has six interrupt sources: two external signals ( int 0 and int 1 ), three timer/counters (timers a, b, and c), and serial interface (serial). an interrupt request flag (if), interrupt mask (im), and vector address are provided for each interrupt source, and an interrupt enable flag (ie) controls the entire interrupt process. interrupt control bits and interrupt servicing: locations $000 through $003 in ram space are reserved for interrupt control bits which can be accessed by ram bit manipulation instructions. the interrupt request flag (if) cannot be set by software. mcu reset initializes the interrupt enable flag (ie) and the if to 0 and the interrupt mask (im) to 1. figure 7 is a block diagram of the interrupt control circuit. table 2 lists interrupt priorities and vector addresses, and table 3 lists the interrupt processing conditions for the six interrupt sources. an interrupt request occurs when the if is set to 1 and im to 0. if the ie is 1 at that point, the interrupt is processed. a priority programmable logic array (pla) generates the vector address assigned to that interrupt source. figure 8 shows the interrupt processing sequence, and figure 9 shows an interrupt processing flowchart. after an interrupt is acknowledged, the previous instruction is completed in the first cycle. the ie is reset in the second cycle, the carry flag, status flag, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. program the jmpl instruction at each vector address to branch the program to the start address of the interrupt program, and reset the if by a software instruction within the interrupt program.
HD404618 series 18 ie if0 im0 if1 im1 ifta imta iftb imtb iftc imtc ifs ims $ 000,0 $ 000,2 $ 000,3 $ 001,0 $ 001,1 $ 001,2 $ 001,3 $ 002,0 $ 002,1 $ 002,2 $ 002,3 $ 003,0 $ 003,1 sequence control ?push pc/ca/st ?reset ie ?jump to vector address priority control logic vector address note: $m, n is at ram address $m, bit number n. figure 7 block diagram of interrupt control circuit table 2 vector addresses and interrupt priorities reset/interrupt priority vector address reset $0000 int 0 1 $0002 int 1 2 $0004 timer a 3 $0006 timer b 4 $0008 timer c 5 $000a serial 6 $000c
HD404618 series 19 table 3 interrupt processing and activation conditions interrupt source interrupt control bit int 0 int 1 timer a timer b timer c serial ie111111 if0 im0 100000 if1 im1 * 10000 ifta imta ** 1000 iftb imtb *** 10 0 iftc imtc **** 10 ifs ims ***** 1 note: bits marked by * can be either 0 or 1. their values have no effect on operation. instruction cycles 123456 instruction execution * ie reset interrupt acceptance execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine vector address generation note: * the stack is accessed and the ie reset after the instruction is executed, even if it is a two-cycle instruction. stacking figure 8 interrupt processing sequence
HD404618 series 20 power on reset = 1 ? reset mcu interrupt request ? execute instruction pc (pc) + 1 ? pc $0002 ? pc $0004 ? pc $0006 ? pc $0008 ? pc $000a ? pc $000c ? ie = 1? accept interrupt ie 0 stack (pc) stack (ca) stack (st) ? int interrupt ? 0 int interrupt ? 1 timer a interrupt ? timer b interrupt ? timer c interrupt ? no yes no yes no yes yes yes yes yes yes no no no no no ? ? ? (serial interrupt) figure 9 interrupt processing flowchart
HD404618 series 21 interrupt enable flag (ie: $000, bit 0): controls the entire interrupt process. it is reset by the interrupt processing and set by the rtni instruction, as shown in table 4. table 4 interrupt enable flag ie interrupt enabled/disabled 0 disabled 1 enabled external interrupts ( int 0 , int 1 ): specified by port mode register a (pmra: $004). the int 1 input can be used as a clock signal input to timer b. timer b increments at each falling edge of the int 1 input. when using int 1 as a timer b external event input, external interrupt mask im1 must be set to prevent the int 1 interrupt request from being accepted (see table 6). to detect the edge of int 0 or int 1 , more than two instruction cycle times are required (2t cyc or 2t subcyc ). external interrupt request flags (if0: $000, bit 2; if1: $001, bit 0): set at the falling edge of the int 0 and int 1 inputs as shown in table 5. table 5 external interrupt request flags if0, if1 interrupt request 0no 1 yes external interrupt masks (im0: $000, bit 3; im1: $001, bit 1): prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as shown in table 6. table 6 external interrupt masks im0, im1 interrupt request 0 enabled 1 disabled (masked) timer a interrupt request flag (ifta: $001, bit 2): set by overflow output from timer a as shown in table 7. table 7 timer a interrupt request flag ifta interrupt request 0no 1 yes
HD404618 series 22 timer a interrupt mask (imta: $001, bit 3): prevents (masks) an interrupt request caused by the timer a interrupt request flag, as shown in table 8. table 8 timer a interrupt mask imta interrupt request 0 enabled 1 disabled (masked) timer b interrupt request flag (iftb: $002, bit 0): set by overflow output from timer b as shown in table 9. table 9 timer b interrupt request flag iftb interrupt request 0no 1 yes timer b interrupt mask (imtb: $002, bit 1): prevents (masks) an interrupt request caused by the timer b interrupt request flag, as shown in table 10. table 10 timer b interrupt mask imtb interrupt request 0 enabled 1 disabled (masked) timer c interrupt request flag (iftc: $002, bit 2): set by overflow output from timer c as shown in table 11. table 11 timer c interrupt request flag iftc interrupt request 0no 1 yes timer c interrupt mask (imtc: $002, bit 3): prevents (masks) an interrupt request caused by the timer c interrupt request flag, as shown in table 12.
HD404618 series 23 table 12 timer c interrupt mask imtc interrupt request 0 enabled 1 disabled (masked) serial interrupt request flag (ifs: $003,bit 0): set when the octal counter counts the eighth transmit clock signal or when data transmit is discontinued by resetting the octal counter, as shown in table 13. table 13 serial interrupt request flag ifs interrupt request 0no 1 yes serial interrupt mask (ims: $003, bit 1): prevents (masks) an interrupt request caused by the serial interrupt request flag, as shown intable 14. table 14 serial interrupt mask ims interrupt request 0 enabled 1 disabled (masked)
HD404618 series 24 operating modes the mcu has five operating modes that are specified by how the clock is used. the functions available in each mode are listed in table 15, and operations are shown in table 16. transitions between operating modes are shown in figure 10. table 17 provides additional information for table 15. table 15 functions available in each operating mode mode name active standby stop watch subactive * 4 activation method reset cancellation, interrupt request sby instruction tma3 = 0, stop instruction tma3 = 1, stop instruction int 0 or timer a interrupt request from watch mode status system oscillator operating operating stopped stopped stopped subsystem oscillator operating operating operating * 1 operating operating instruction execution ( cpu ) operating stopped stopped stopped operating peripheral function interrupt( per ) operating operating stopped stopped operating clock function interrupt ( clk ) operating operating stopped operating * 2 operating * 2 ram operating retained retained retained operating registers/ flags operating retained reset retained operating i/o operating retained high impedance * 3 retained * 3 operating * 3 cancellation method reset input, stop/sby instruction reset input, interrupt request reset input reset input, int 0 or timer a interrupt request reset input, stop/sby instruction notes: 1. to reduce current dissipation, stop all oscillation in external circuits. 2. refer to the interrupt frame section for details. 3. refer to table 17. 4. subactive mode is an optional function, specify it on the function option list. 5. in the watch and subactive modes, the mcu requires a 32.768-khz crystal oscillator.
HD404618 series 25 system clock ( cpu ) operating stopped non-time-base peripheral function clock ( per ) operating active mode standby mode subactive mode stopped watch mode (tma3 = 1) stop mode (tma3 = 0) table 16 operations in low-power dissipation modes function stop mode watch mode * 3 standby mode subactive mode * 2, 3 cpu reset retained retained op ram retained retained retained op timer a reset op op op timer b reset stopped op op timer c reset stopped op op serial interface reset stopped * 4 op op lcd reset op op op dtmf reset reset stopped reset i/o reset * 1 retained retained op notes: op indicates operating. 1. output pins are at high impedance. 2. subactive mode is an optional function specified on the function option list. 3. in the watch and subactive modes, the mcu requires a 32.768 khz crystal oscillator. 4. transmission/reception is activated if a clock is input in external clock mode. (however, interrupts stop.)
HD404618 series 26 reset f : f : ? : ? : ? : cpu clk per osc x operating operating stopped f f cyc cyc f : f : ? : ? : ? : cpu clk per osc x operating operating stopped f f sub cyc f : f : ? : ? : ? : cpu clk per osc x operating operating f f f cyc cyc cyc f : f : ? : ? : ? : cpu clk per osc x operating operating f f f cyc sub cyc f : f : ? : ? : ? : cpu clk per osc x stopped operating f f f sub sub sub f : f : ? : ? : ? : cpu clk per osc x stopped operating stopped stopped stopped f : f : ? : ? : ? : cpu clk per osc x stopped operating stopped f stopped sub f : f : ? : ? : ? : cpu clk per osc x stopped operating stopped f stopped sub standby mode stop mode (tma3 = 0) watch mode subactive mode (tma3 = 1) (tma3 = 1, lson = 0) (tma3 = 1, lson = 1) (tma3 = 0) sby (standby) interrupt timers a, b, c, serial, int , int 0 1 sby (standby) interrupt stop stop int , timer a 0 int , timer a 0 stop stop/sby (lson = 1) 1. 2. 3. 4. f : f : f : f : ? : ? : ? : lson: dton: cyc sub osc x main oscillation frequency suboscillation frequency for time-base f /4 f /8 system clock clock for time-base clock for other peripheral functions low speed on flag direct transfer on flag osc x cpu clk per active mode timers a, b, c, serial, int , int 0 1 * 4 * 2 * 3 * 1 notes: * 1 time-base interrupt stop/sby (dton = 1, lson = 0) stop/sby (dton = 0, lson = 0) dton is not affected figure 10 mcu status transitions table 17 i/o status in low-power dissipation modes output input standby mode, watch mode stop mode active mode, subactive mode d 0 ? 9 retained high impedance input enabled d 10 ? 13 input enabled r0?3 retained high impedance input enabled
HD404618 series 27 active mode: the mcu operates according to the clock generated by the system oscillators osc 1 and osc 2 . standby mode: the mcu enters standby mode when the sby instruction is executed from active mode. in this mode, the oscillators, interrupts, timer/counters, and serial interface continue to operate, but all instruction execution-related clocks stop. the stopping of these clocks stops the cpu, retaining all ram and register contents and maintaining the current i/o pin status. standby mode is terminated by a reset input or an interrupt request. if it is terminated by reset input, the mcu is reset as well. after an interrupt request, the mcu enters active mode and resumes, executing the next instruction after the sby instruction. if the interrupt enable flag is 1, that interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. a flowchart of operation in standby mode is shown in figure 11.
HD404618 series 28 standby oscillator: active peripheral clocks: active all other clocks: stopped reset = 1 ? no yes if0 = 1 ? no yes im0 = 0 ? if1 = 1 ? no yes im1 = 0 ? ifta = 1 ? no yes imta = 0 ? iftb = 1 ? no yes imtb = 0 ? iftc = 1 ? no yes imtc = 0 ? ifs = 1 ? no yes ims = 0 ? no yes no yes no yes no yes no yes no yes (sby only) (sby only) (sby only) (sby only) watch oscillator: stopped sub-oscillator: active peripheral clocks: stopped all other clocks: stopped restart processor clocks reset mcu execute next instruction accept interrupt execute next instruction (active mode) restart processor clocks no yes if = 1, im = 0, and ie = 1 ? figure 11 mcu operation flowchart in watch and standby modes stop mode: the mcu enters stop mode if the stop instruction is executed in active mode when tma3 = 0. in this mode, the system oscillator stops, which stops all mcu functions as well. stop mode is terminated by a reset input as shown in figure 12. reset must be high for at least one t rc to stabilize oscillation (refer to the ac characteristics section). when the mcu restarts after stop mode is cancelled, all ram contents are retained, but the accuracy of the contents of the accumulator, b register, w register, x/spx register, y/spy register, carry flag, and serial data register cannot be guaranteed.
HD404618 series 29 stop mode oscillator internal clock reset stop instruction execution t > t (stabilization time) rc t res res figure 12 timing of stop mode cancellation watch mode: the mcu enters watch mode if the stop instruction is executed in active mode when tma3 = 1, or if the stop or sby instruc-tion is executed in subactive mode. watch mode is terminated by a reset input or a timer-a/ int 0 interrupt request. for details of reset input, refer to the stop mode section. when terminated by a timer-a/ int 0 interrupt request, the mcu enters active mode if lson is 0, or subactive mode if lson is 1. after an interrupt request is generated, the time required to enter active mode is t rc for a timer a interrupt, and t x (where t + t rc < t x < 2t + t rc ) for an int 0 interrupt, as shown in figure 13. operation during mode transition is the same as that at standby mode cancellation (figure 12). active mode watch mode active mode oscillation stabilization period interrupt strobe int interrupt request generation (during the transition from watch mode to active mode only) 0 ttt rc tx t = 2 t rc : interrupt frame length t rc : oscillation stabilization period figure 13 interrupt frame subactive mode: the cpu operates with a clock generated by the x1 and x2 oscillation circuits. functions that can operate in subactive mode are listed in table 16. when the stop or sby instruction is executed in subactive mode, the mcu enters either watch or active mode, depending on the statuses of
HD404618 series 30 lson and dton. the dton flag can only be set in subactive mode; it is automatically reset after a transition to active mode. subactive mode is an optional function that the user must specify on the function option list. interrupt frame: in watch and subactive modes, clk is supplied for timer a and the i nt 0 circuit. prescaler w and timer a operate as time bases to generate interrupt frame timing. three interrupt frame cycles (t) can be selected by the settings of the miscellaneous register, as shown in figure 14. in watch and subactive modes, timer a and int 0 interrupts are generated in synchronism with the interrupt frame. an interrupt request is generated at the interrupt strobe timing, except when the mcu enters active mode from watch mode. the int 0 falling edge is acknowledged regardless of the interrupt frame, but the interrupt is executed simultaneously with the next interrupt strobe. timer a generates an overflow and interrupt request at the timing of an interrupt strobe. t rc mis: $00c mis1 mis0 mis2 refer to table 20 t selection rc mis bit 1 bit 0 t 0 0 15.625 ms 0 0 1 1 1 0.24414 ms 62.5 ms 31.25 ms 0.24414 ms 7.8125 ms 0.12207 ms * 2 * 1 not used 400/800-khz ceramic oscillator external clock input oscillation circuit condition * 1 notes: 1. 2. the value of t applies only when using a 32.768-khz oscillator. only direct transfer. rc 1 figure 14 miscellaneous register direct transfer: by controlling the dton, the mcu would be placed directly from subactive to active mode. the detailed procedure is as follows: set the dton flag in subactive mode while lson = 0. execute the stop or sby instruction. after the oscillation stabilization time (a fixed value), the mcu will move automatically from subactive to active mode. note that dton ($020, bit 3) is valid only in subactive mode. when the mcu is in active mode, this flag is always at reset. the transition time (t d ) from subactive to active mode is t rc < t d < t + t rc .
HD404618 series 31 subactive mode interrupt strobe direct transfer timing internal execution time oscillation stabilization time active mode t t rc t: interrupt frame length t : oscillation stabilization period rc stop/sby execution (lson = 0, dton = 1) (< t) figure 15 direct transfer timing mcu operating sequence: the mcu operates in the sequence shown in figures 16 to 18. it is reset by an asynchronous reset input, regardless of its state. the low-power mode operation sequence is shown in figure 18. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt flags are cleared or all interrupts are masked. power on reset = 1 ? reset mcu mcu operation cycle no yes figure 16 mcu operating sequence (power on)
HD404618 series 32 mcu operation cycle if = 1 ? instruction execution sby/stop instruction ? pc next location pc vector address low-power mode operation cycle ie ; stack (pc), (ca), (st) im = 0 and ie = 1 ? ? ? ? yes no no yes yes no interrupt request flag interrupt mask interrupt enable flag ? 0 if: im: ie: program counter carry flag status flag pc: ca: st: figure 17 mcu operating sequence (mcu operation cycle)
HD404618 series 33 low-power mode operation cycle if = 1 im = 0 ? hardware nop execution ? pc next iocation mcu operation cycle standby/watch mode if = 1 im = 0 ? hardware nop execution pc next iocation ? instruction execution stop mode no yes no yes for if and im operation, refer to figure 12. figure 18 mcu operating sequence (low-power mode operation) notes on use: in subactive mode, the timer a interrupt request or the external interrupt request ( int 0 ) occurs in synchronism with the interrupt strobe. if the stop or sby instruction is executed at the same time with the interrupt strobe, these interrupt requests will be cancelled and the corresponding interrupt request flags (ifta, if0) will not be set. in subactive mode, do not use the stop or sby instruction at the time of the interrupt strobe.
HD404618 series 34 when the mcu is in watch mode or subactive mode, if the high level period before the falling edge of int 0 is shorter than the interrupt frame, int 0 is not detected. also, if the low level period after the falling edge of int 0 is shorter than the interrupt frame, int 0 is not detected. edge detection is shown in figure 19. the level of the int 0 signal is sampled by a sampling clock. when this sampled value changes to low from high, a falling edge is detected. in figure 20, the level of the int 0 signal is sampled by an interrupt frame. in (a) the sampled value is low at point a, and also low at point b. therefore, a falling edge is not detected. in (b), the sampled value is high at point a, and also high at point b. a falling edge is not detected in this case either. when the mcu is in watch mode or subactive mode, keep the high level and low level period of int 0 longer than interrupt frame. high low int sampling 0 low figure 19 edge detection a: low b: low int interrupt frame 0 a: high b: high int interrupt frame 0 (a) high level period (b) low level period figure 20 sampling example
HD404618 series 35 internal oscillator circuit figure 21 shows a block diagram of the internal oscillator circuit. a ceramic oscillator can be connected to osc 1 and osc 2 , and a 32.768-khz crystal oscillator can be connected to x1 and x2. the system oscillator can also be operated by an external clock. f osc x2 x1 subsystem oscillator divider (1/4) divider (1/8) mode control circuit timing generator osc f x cyc f sub f timing generator system clock (? ) cpu system clock (? ) per timer-base clock (? ) clk osc system oscillator 1 2 figure 21 internal oscillator circuit $ % & ' , - ! "# $ ' ( )* + . / 0 d 0 reset osc 2 osc 1 v cc vt ref comp 1 /d 13 test x1 x2 gnd sck /r0 0 gnd figure 22 layout of crystal and ceramic oscillators
HD404618 series 36 table 18 oscillator circuit examples circuit configuration circuit constants external clock operation (osc 1 , osc 2 ) external oscillator osc open 1 osc 2 ceramic oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f ceramic gnd ceramic oscillator: csb400p22, csb400p (murata) r f = 1 m w 20% c 1 = c 2 = 220 pf 5% ceramic oscillator: csb800j122, csb800j(murata) r f = 1 m w 20% c 1 = c 2 = 220 pf 5% crystal oscillator x1 c 1 2 c x2 crystal gnd l s c r s c 0 crystal: 32.768 khz: mx38t (nippon denpa kogyo) r s = 14 k w c 0 = 1.5 pf c 1 = 20 pf 20% c 2 = 20 pf 20% notes: 1. the circuit constants given above are recommended values provided by the oscillator manufacturer. since they may be affected by stray capacitances from the oscillator or board, consult the crystal or ceramic oscillator manufacturer to determine the actual circuit parameters required. 2. wiring between the osc 1 /osc 2 pins (x1, x2 pins) and other elements must be as short as possible, and must not cross other wiring. refer to the recommended layout of the crystal and ceramic oscillator in figure 22. 3. if a 32.768-khz crystal oscillator is not used, fix the x1 pin to v cc and leave the x2 pin open.
HD404618 series 37 input/output the mcu provides 26 input/output pins and 4 input pins, including 10 high-current pins (15 ma, max.). a program-controlled pull-up mos transistor is provided for each input/output pin. the output buffer is turned on and off by the data control register (dcr) during input through an input/output pin. i/o pin circuit types are shown in table 19. d ports (d 0 ? 13 ): consist of ten 1-bit input/output pins and four input pins. pins d 0 ? 9 are high-current i/o pins (15 ma, max.). the sum current of the pins can go up to 100 ma. these pins are set by the sed and sedd instructions, reset by the red and redd instructions, and tested by the td and tdd instructions. output data is stored in the port data register. the on/off status of the output buffer is controlled by d port data control registers (dcrb, dcrc, and dcrd) that are mapped to the memory address area. pins d 10 ? 13 are input-only pins. two operating modes are available to pins d 12 and d 13 : digital input mode and analog input mode. the operating modes are set by bits 0 and 1 of port mode register b (pmrb). in the digital input mode, these pins can be used as input pins with the same input characteristics as the i/o pins. in the analog input mode, the result of a comparison with the reference voltage can be read as input data. the reference voltage is input by the d 11 /vc ref pin. r ports: consist of sixteen 4-bit i/o ports. data is input to these ports by the lar and lbr instructions and output from them by the lra and lrb instructions. the on/off status of the output buffers of the r ports are controlled by r port data control registers (dcr0 dcr3) that are mapped to memory addresses. pins r0 0 , r0 1 , and r0 2 are multiplexed with pins sck , si, and so, respectively. pins r3 1 , r3 2 , and r3 3 are multiplexed with timo, int 0 , and int 1 , respectively. refer to figure 24. pull-up mos transistor control: a program-controlled pull-up mos transistor is provided for each input/output pin. the on/off status of all these transistors is controlled by bit 3 of port mode register b (pmrb), and the on/off status of an individual transistor can also be controlled by the port data register (pdr) of the corresponding pin. this enables on/off control of each individual pin. refer to table 20. the on/off status of each transistor and the peripheral function mode of each pin can be set independently. how to deal with unused i/o pins: i/o pins that are not needed by the user system must be connected to v cc to prevent lsi malfunctions due to noise. these pins must either be pulled up to v cc by their pull-up transistors or by resistors of about 100 k w .
HD404618 series 38 table 19 circuit configurations of i/o pins i/o pin type circuit applicable pins common i/o pin (with pull-up mos transistor) v cc v cc input control signal input data output data pdr dcr pull-up control signal d 0 ? 9 r0 0 ?0 3 r1 0 ?1 3 r2 0 ?2 3 r3 0 ?3 3 v cc v cc sck output data sck (internal) dcr pull-up control signal sck output pin (with pull-up mos transistor) v cc v cc output data so or timo dcr pull-up control signal so, timo input pin v cc pdr pull-up control signal int 0 , int 1 si input control signal input data d 10 d 11 /vc ref vc ref + analog input input control input data mode select signal d 12 /comp 0 d 13 /comp 1 (multiplexed with analog inputs) note: refer to table 20, note 3 concerning r0 2 /so.
HD404618 series 39 mpx pin comparator + vc ref mode register internal bus figure 23 configuration of d 12 and d 13
HD404618 series 40 port mode register a: $004 (pmra) 321 0 r0 /so pin mode selection 2 r0 /si pin mode selection 1 r3 / int pin mode selection 2 r3 / int pin mode selection 3 0 1 port selection bit 3 0 1 r3 int 3 pmra 1 bit 2 pmra 0 1 r3 int 2 0 port selection bit 1 pmra 0 1 r0 si 1 port selection bit 0 pmra 0 1 r0 so 2 port selection pull-up mos on/off bit 3 0 1 off on pmrb bit 2 pmrb 0 1 r3 timo 1 port selection bit 1 pmrb 0 1 d comp 1 13 port selection bit 0 pmrb 0 1 d comp 0 12 port selection d /comp0 pin mode selection 12 13 1 0 321 port mode register b: $012 (pmrb) d /comp1 pin mode selection r3 /timo pin mode selection pull-up mos on/off selection port selection bit 3 0 1 r0 sck 0 smr serial mode register: $005 (smr) r0 / sck pin mode selection 0 321 0 figure 24 i/o switching mode registers
HD404618 series 41 table 20 programmable i/o circuits pmrb bit 3 (pmrb3) 0 1 dcr 01 01 pdr 01010101 cmos buffer pmos (a) on on nmos (b) on on pull-up mos transistor on?n notes: 1. ? off 2. various i/o methods can be selected by different combinations of settings of the above mode registers (pmrb3, dcr, pdr). 3. the pmos (a) transistor of the r1 2 /so pin can be turned off by setting bit 2 of the miscellaneous register (mis) to 1. mis bit 2 r0 2 /so pin pmos (a) 0on 1 off 4. the relationships between dcrs and pins are as shown below. dcr bit 3 bit 2 bit 1 bit 0 dcr0 r0 3 r0 2 r0 1 r0 0 dcr1 r1 3 r1 2 r1 1 r1 0 dcr2 r2 3 r2 2 r2 1 r2 0 dcr3 r3 3 r3 2 r3 1 r3 0 dcrb d 3 d 2 d 1 d 0 dcrc d 7 d 6 d 5 d 4 dcrd d 9 d 8
HD404618 series 42 pmrb3 input control signal v cc pull-up mos transistor dcr pdr input data nmos (b) pmos (a) v cc figure 25 i/o buffer configuration
HD404618 series 43 timers the mcu has two prescalers (s and w) and three timer/counters (a, b, and c). figures 26, 27 and 28 show their diagrams. prescaler s: eleven-bit counter that inputs the system clock signal. after being initialized to $000 by mcu reset, prescaler s divides the system clock. prescaler s keeps counting, except at mcu reset and in the stop and watch modes. of the prescaler s outputs, timer a input clock, timer b input clock, timer c input clock, and serial interface transmit clock are selected by timer mode register a (tma), timer mode register b (tmb), timer mode register c (tmc), and the serial mode register (smr), respectively. prescaler w: five-bit counter that inputs the x1 input clock signal divided by eight. prescaler w output can be selected as a timer a input clock by timer mode register a (tma). timer a: eight-bit timer that can be used as a clock time-base (figure 26). it is initialized to $00 and incremented at each clock input. if an input clock is applied to timer a after it has reached $ff, an overflow that sets the timer a interrupt request flag (ifta: $001, bit 2) is generated, and timer a restarts from $00. timer a is used to generate regular interrupts (every 256 clocks) for measuring times between events. it can also be used as a clock time-base when bit 3 of timer mode register a (tma) is set to 1. the timer is driven by the 32-khz oscillator clock frequency divided by prescaler w, and the clock input to timer a is controlled by tma. in this case, prescaler w and timer a can be initialized to $00 by software. 1/4 1/2 32.768-khz oscillator system clock prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f sub 1/2 t subcyc (t subcyc ) per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? 2 8 16 32 ? ? ? ? f sub figure 26 timer a block diagram
HD404618 series 44 timer b (tcbl and tlrl: $00a, tcbu and tlru: $00b): eight-bit write-only timer load register (tlrl and tlru) and read-only timer counter (tcbl and tcbu) located at the same addresses. the eight-bit configuration consists of lower and upper 4-bit digits located at sequential addresses. a block diagram of timer b is shown in figure 27. timer counter b is initialized by writing to timer load register b (tlr). in this case, the lower digit must be written to first. the contents of tlr are loaded into the timer counter at the same time the upper digit is written to, initializing the timer counter. tlr is initialized to $00 by mcu reset. the count of timer b is obtained by reading timer counter b. in this case, the upper digit must be read first; the count is latched when the upper digit is read. an auto-reload function, input clock source, and prescaler division ratio of timer b depend on the state of timer mode register b (tmb). when an external event input is used as the input clock source of tmb, the r3 3 / int 1 pin must be set to int 1 by setting port mode register a (pmra: $004). timer b is initialized to the value set in tmb by software, and is then incremented by one each clock input. if an input is applied to timer b after it has reached $ff, an overflow is generated. in this case, if the auto-reload function is enabled, timer b is initialized to its initial value; if auto-reload is disabled, the timer is initialized to $00. the overflow sets the timer b interrupt request flag (iftb: $002, bit 0).
HD404618 series 45 system clock int 1 selector prescaler s (pss) clock timer counter register bu (tcbu) timer counter register bl (tcbl) timer counter b (tcb) timer load register bu (tlru) timer load register bl (tlrl) timer mode register b (tmb) timer b interrupt request flag (iftb) f cyc /f sub (t cyc /t subcyc ) 3 internal data bus 2 4 8 32 128 512 2048 ? ? ? ? ? ? ? free-running control overflow figure 27 timer b block diagram timer c (tccl and tcrl: $00e, tccu and tcru: $00f): eight-bit write-only timer load register (tcrl and tcru) and read-only timer counter (tccl and tccu) located at the same addresses. the eight-bit configuration consists of lower and upper 4-bit digits located at sequential addresses. the operation of timer c is basically the same as that of timer b. the auto-reload function and prescaler division ratio of timer c depend on the state of timer mode register c (tmc). timer c is initialized to the value set in tmc by software, and is then incremented by one at each clock input. if an input is applied to timer c after it has reached $ff, an overflow is generated. in this case, if the auto-reload function is enabled, timer c is initialized to its initial value; if auto-reload is disabled, the timer is initialized to $00. the overflow sets the timer c interrupt request flag (iftc: $002, bit 2). timer c also functions as a watchdog timer. if a program routine runs out of control and an overflow is generated while the watchdog on (wdon) flag is set, the mcu is reset. this error can be detected by having the program control timer c reset before timer c reaches $ff. the wdon can only have 1 written to it ; it is cleared to 0 only by mcu reset. timer mode register a (tma: $008): four-bit write-only register that controls timer a as shown in table 21.
HD404618 series 46 watchdog on flag (wdon) system reset signal timer c interrupt request flag (iftc) timer output control logic timer counter register cu (tccu) timer counter register cl (tccl) clock timer counter c (tcc) selector system clock prescaler s (pss) overflow internal data bus timer load register cu (tcru) timer load register cl (tcrl) timer mode register c (tmc) free-running /reload control watchdog timer control logic timo 2 4 8 32 128 512 1024 2048 3 f cyc /f sub (t cyc /t subcyc ) figure 28 timer c block diagram
HD404618 series 47 table 21 timer mode register a tma bit 3 bit 2 bit 1 bit 0 source prescaler, input clock period, operating mode 0 0 0 0 pss, 2048 t cyc timer a mode 1 pss, 1024 t cyc 1 0 pss, 512 t cyc 1 pss, 128 t cyc 1 0 0 pss, 32 t cyc 1 pss, 8 t cyc 1 0 pss, 4 t cyc 1 pss, 2 t cyc 1 0 0 0 psw, 32 t subcyc time-base mode 1 psw, 16 t subcyc 1 0 psw, 8 t subcyc 1 psw, 2 t subcyc 1 0 0 psw, 1/2 t subcyc 1 not used 1 0 psw, tca reset 1 notes: 1. t subcyc = 244.14 m s (when 32.768-khz crystal oscillator is used) 2. timer counter overflow output period(s) = input clock period(s) 256 3. if psw or tca reset is selected while the lcd is operating, lcd operation halts (power switch goes off). when lcd is connected for display, the psw and tca reset periods must be set in the program to the minimum. 4. in time base mode, the timer counter overflow output cycle must be greater than half of the interrupt frame period (t/2 = t rc ). if 1/2 t subcyc is selected, t rc must be 7.8125 ms ((mis1, mis0) = (0, 1), see figure 14). 5. the division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur.
HD404618 series 48 t (tcr + 1) t 256 t t (256 ?tcr) tmc3 = 0 period of clock input to the counter (table 23) value of timer load register c (0?55) note: this waveform is always fixed low when tcr = $ff. tmc3 = 1 t: tcr: figure 29 variable-duty pulse output waveform timer mode register b (tmb: $009): four-bit write-only register that selects the auto-reload function, the prescaler division ratio, and input clock source as shown in table 22. timer mode register b is initialized to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle. timer b initialization set by writing to tmb must be done after a mode change becomes valid. table 22 timer mode register b tmb bit 3 auto-reload function 0 disabled 1 enabled tmb bit 2 bit 1 bit 0 prescaler division ratio, clock input source 00 0 ? 2048 00 1 ? 512 01 0 ? 128 01 1 ? 32 10 0 ? 8 10 1 ? 4 11 0 ? 2 11 1 int 1 (external event input)
HD404618 series 49 timer mode register c (tmc: $00d): four-bit write-only register that selects the auto-reload function and prescaler division ratio as shown in table 23. timer mode register c is initialized to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle. timer c initialization set by writing to tmc must be done after a mode change becomes valid. table 23 timer mode register c tmc bit 3 auto-reload function 0 disabled 1 enabled tmc bit 2 bit 1 bit 0 prescaler division ratio, clock input source 00 0 ? 2048 00 1 ? 1024 01 0 ? 512 01 1 ? 128 10 0 ? 32 10 1 ? 8 11 0 ? 4 11 1 ? 2
HD404618 series 50 note on use when using the timer output as pwm output, note the following point. from the update of the timer write register untill the occurrence of the overflow interrupt, the pwm output differs from the period and duty settings, as shown in table 24. the pwm output should therefore not be used until after the overflow interrupt following the update of the timer write register. after the overflow, the pwm output will have the set period and duty cycle. table 24 pwm output following update of timer write register pwm output mode timer load register is updated during high pwm output timer load register is updated during low pwm output free running timer load register updated to value n interrupt request timer load register updated to value n interrupt request t (255 ?n) t (n + 1) t (n' + 1) t (255 ?n) t (n + 1) reload timer load register updated to value n interrupt request timer load register updated to value n interrupt request t t (255 ?n) t t t (255 ?n) t
HD404618 series 51 serial interface the mcu has a clock-synchronous serial interface which transmits and receives 8-bit data. the serial interface consists of a serial data register (sr), serial mode register (smr), port mode register a (pmra), octal counter, and multiplexers (see figure 30). the r0 0 / sck pin and the transmit clock are controlled by writing to the smr. the transmit clock shifts the contents of the sr, which can be read and written to by software. the serial interface is activated by the sts instruction. the octal counter is reset to 000 by this instruction, starts counting at the falling edge of the transmit clock ( sck ), and it increments at the rising edge of the clock. a serial interrupt request flag is set when the eighth transmit clock signal is input (the serial interface is reset) or when serial transmission is discontinued (the octal counter is reset). internal data bus port mode register a (pmra) sck selector system clock f cyc /f sub (t cyc /t subcyc ) prescaler s (pss) i/o control logic 3 serial mode register (smr) clock serial data register (sr) serial interrupt request flag (ifs) selector 1/2 si so octal counter (oc) i/o control logic transfer control signal 2 8 32 128 512 2048 ? ? ? ? ? ? figure 30 serial interface block diagram serial mode register (smr: $005): four-bit write-only register that controls the r0 0 / sck pin, prescaler division ratio, and transmit clock source (table 25 and figure 31). writing to this register initializes the serial interface.
HD404618 series 52 a write signal input to the serial mode register discontinues the input of the transmit clock to the serial data register and octal counter. therefore, if a write is performed during data transmission, the octal counter is reset to 000 to stop transmission, and at the same time, the serial interrupt request flag is set. write operations are valid from the second instruction execution cycle, so the sts instruction must be executed after at least two cycles have been executed. the serial mode register is initialized to $0 by mcu reset. table 25 serial mode register smr bit 3 r0 0 / sck pin 0r0 0 port input/output pin 1 sck input/output pin smr transmit clock bit 2 bit 1 bit 0 r0 0 / sck pin clock source prescaler division ratio system clock division ratio 000 sck output prescaler ? 2048 ? 4096 001 sck output prescaler ? 512 ? 1024 010 sck output prescaler ? 128 ? 256 011 sck output prescaler ? 32 ? 64 100 sck output prescaler ? 8 ? 16 101 sck output prescaler ? 2 ? 4 110 sck output system clock ? 1 111 sck input external clock pmra3 pmra2 pmra1 pmra: $004 smr3 smr2 smr1 smr0 smr: $005 r0 /so pin mode selection transmit clock selection r0 / sck pin mode selection 0 r0 /si pin mode selection 2 1 pmra0 figure 31 configurations and functions of the mode registers
HD404618 series 53 serial data register (srl: $006, sru: $007): eight-bit read/write register separated into upper and lower digits located at sequential addresses. data in this register is output from the so pin, lsb first, in synchronism with the falling edge of the transmit clock, and data is input lsb first through the si pin at the rising edge of the transmit clock. input/output timing is shown in figure 32. data cannot be read or written during serial data transmission. if a read/write occurs during transmission, the accuracy of the resultant data cannot be guaranteed. lsb msb 12 345 678 transmit clock serial output data serial input data latch timing figure 32 serial interface timing selecting and changing operating mode: table 26 lists the serial interface operating modes. to select an operating mode, use one of these combinations of pmr and smr settings; to change the operating mode, always initialize the serial interface internally by writing to the smr. table 26 serial interface operating modes smr pmra bit 3 bit 1 bit 0 operating mode 1 0 0 continuous clock output mode 1 0 1 transmit mode 1 1 0 receive mode 1 1 1 transmit/receive mode serial interface operation: three operating modes are provided for the serial interface; transitions between them are shown in figure 33. in sts waiting state, the serial interface is initialized and the transmit clock is ignored. if the sts instruction is then executed, the serial interface enters transmit clock wait state. in transmit clock wait state, input of the transmit clock increments the octal counter, shifts the serial clock register, and activates serial transmission. however, note that if clock output mode is selected, the transmit clock is continuously output but data is not transmitted.
HD404618 series 54 during transmission, the input of eight clocks or the execution of the sts instruction sets the octal counter to 000, and the serial interface enters transmit clock wait state. if the state changes from transmit to another state, the serial interrupt request flag is set by the octal counter reaching 000. octal counter = 000 transmit clock disabled sts instruction wait state transmit clock 8 transmit clocks (external clock) sts instruction ? (ifs 1) (octal counter = 000) 1 transmit clock wait state transfer state (octal counter 000) smr write sts instruction smr write 8 transmit clocks (internal clock) (ifs 1) ? (ifs 1) ? figure 33 serial interface mode transitions in this state, if the internal clock has been selected, the transmit clock is output in answer to the execution of the sts instruction, but serial transmission is inhibited after the eighth clock is output. if port mode register a (pmra) is written to in transmit clock wait state or during transmission, the serial mode register (smr) must be written to, to initialize the serial interface. the serial interface then enters sts wait state. if the serial interface shifts from transfer state to another state, the octal counter returns to 000, setting the serial interrupt request flag. transmit clock error detection: the serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transmission. a transmit clock error of this type can be detected as shown in figure 34. if more than eight transmit clocks are input in transmit clock wait state, the serial interface state changes to transfer, transmit clock wait, then back to transfer. if the serial interface is set to sts wait state by writing data to the smr after the serial interrupt request flag has been reset, the flag is set again.
HD404618 series 55 transmission completion (ifs 1) ? interrupts inhibited ifs 0 ? smr write ifs = 1 ? normal termination transmit clock error processing no yes figure 34 transmit clock error detection note on use: the serial interrupt request flag might not be set if the status is changed from transfer by the execution of an smr write or sts instruction during the first period that the transmit clock is low. to prevent this, program a check that the sck pin is at 1 (by executing an input instruction for the r1 port) before the execution of an smr write or sts instruction, to ensure that the serial interrupt request flag is set.
HD404618 series 56 liquid crystal display (lcd) the mcu has an lcd controller and driver which drive 4 common signal pins and 32 segment signal pins. the controller consists of a ram area in which display data is stored, a display control register (lcr), and a duty/clock control register (lmr), as shown in figure 37. four duties and the lcd clock are program-controllable, and a built-in dual-port ram ensures that display data can be automatically transmitted to the segment signal pins without program intervention. if a 32-khz oscillation clock is selected as the lcd clock source, the lcd can be used even in watch mode, in which the system clock stops. v cc power switch v 1 v 2 v 3 gnd lcd power control circuit lcd common driver display on/off display area lcd duty/clock control register (lmr: $014) (dual-port ram) lcd control register (lcr: $013) lcd segment driver lcd clock $050 $06f ram area duty cycle selection clock selection 22 3 1 lcd clock seg32 seg2 seg1 com4 com3 com2 com1 divided system clock output (cl1?l3) divided 32-khz clock output (cl0) lcd: liquid crystal display 12 figure 35 liquid crystal display block diagram lcd data area and segment data ($050?$06f): figure 36 shows the configuration of lcd ram area. each bit of the storage area corresponds to one of four types of duties. if data is written to an area corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display data.
HD404618 series 57 bit 3 bit 2 bit 1 bit 0 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 $050 $051 $052 $053 $054 $055 $056 $057 $058 $059 $05a $05b $05c $05d $05e $05f com4 com3 com2 com1 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 bit 3 bit 2 bit 1 bit 0 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 $060 $061 $062 $063 $064 $065 $066 $067 $068 $069 $06a $06b $06c $06d $06e $06f com4 com3 com2 com1 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 figure 36 configuration of lcd ram area lcd control register (lcr: $013): three-bit write-only register which controls lcd blanking, the turning on and off of the lcd? power supply division resistor, and display in watch and subactive modes (see table 27). blank/display blank: segment signals are turned off regardless of lcd ram data setting. display: lcd ram data is output as segment signals. power switch on/off off: the power switch is off. on: the power switch is on and v 1 is v cc . watch/subactive mode display off: in watch and subactive modes, all common and segment pins are grounded and the liquid crystal power switch is turned off. on: in watch and subactive modes, lcd ram data is output as segment signals.
HD404618 series 58 table 27 lcd control register lcr lcr lcr bit 2 display in watch mode or subactive mode bit 1 power switch on/off bit 0 blank/display 0 off 0 off 0 blank 1 on 1 on 1 display note: when using an lcd in watch mode or subactive mode, use the divided output of a 32-khz oscillator as the lcd clock and set bit 2 of the lcr to 1. if using the divided output of the system clock as the lcd clock, always set bit 2 of the lcr to 0. lcd duty/clock control register (lmr: $014): four-bit write-only register which selects the display duty and lcd clock source, as shown in table 28. table 28 lcd duty/clock control register lmr bit 3 bit 2 bit 1 bit 0 duty selection/input clock selection 0 0 1/4 duty cycle 0 1 1/3 duty cycle 1 0 1/2 duty cycle 1 1 static 0 0 cl0 (32.768/64 khz when using 32.768-khz oscillator) 0 1 cl1 (f cyc /256) 1 0 cl2 (f cyc /2048) 1 1 cl3 (refer to table 29) note: f cyc is the divided system clock output.
HD404618 series 59 210 lcd control register: $013 (lcr) blank/display power switch on/off (not used) display on/off in watch mode duty cycle input clock 3210 lcd duty/clock control register: $014 (lmr) figure 37 lcd control and lcd mode registers
HD404618 series 60 table 29 lcd frame periods for different duties static duty lmr instruction cycle time bit 3 0 bit 2 0 bit 3 0 bit 2 1 bit 3 1 bit 2 0 bit 3 1 bit 2 1 cl0 cl1 cl2 cl3 * 10 m s 512 hz 390.6 hz 48.8 hz 24.4 hz/64 hz 5 m s 512 hz 781.2 hz 97.6 hz 48.8 hz/64 hz 1/2 duty lmr instruction cycle time bit 3 0 bit 2 0 bit 3 0 bit 2 1 bit 3 1 bit 2 0 bit 3 1 bit 2 1 cl0 cl1 cl2 cl3 * 10 m s 256 hz 195.3 hz 24.4 hz 12.2 hz/32 hz 5 m s 256 hz 390.6 hz 48.8 hz 24.4 hz/32 hz 1/3 duty lmr instruction cycle time bit 3 0 bit 2 0 bit 3 0 bit 2 1 bit 3 1 bit 2 0 bit 3 1 bit 2 1 cl0 cl1 cl2 cl3 * 10 m s 170.6 hz 130.2 hz 16.3 hz 8.1 hz/21.3 hz 5 m s 170.6 hz 260.4 hz 32.6 hz 16.2 hz/21.3 hz 1/4 duty lmr instruction cycle time bit 3 0 bit 2 0 bit 3 0 bit 2 1 bit 3 1 bit 2 0 bit 3 1 bit 2 1 cl0 cl1 cl2 cl3 * 10 m s 128 hz 97.7 hz 12.2 hz 6.1 hz/16 hz 5 m s 128 hz 195.4 hz 24.4 hz 12.2 hz/16 hz note: * the division ratio depends on the value of bit 3 of timer mode register a (tma3): the first value is for tma3 = 0 and the second is for tma3 = 1. when tma3 = 0, cl3 = f cyc duty cycle/4096. when tma3 = 1, cl3 = 32.768 khz duty cycle/512
HD404618 series 61 large liquid-crystal panel drive and v lcd : to drive a large-capacity lcd, decrease the resistance of the built-in division resistors by attaching external resistors in parallel, as shown in figure 38. the size of these resistors cannot be simply calculated from the lcd load capacitance because the matrix configuration of the lcd complicates the paths of charge/discharge currents flowing through the capacitors. the resistance will also vary with lighting conditions. this size must be determined by trial and error, taking into account the power dissipation of the device using the lcd, but a resistance of 1 to 10 k w would usually be suitable. (another effective method is to attach capacitors of 0.1 to 0.3 m f.) always turn off the power switch (set bit 1 of the lcr to 0) before changing the liquid crystal drive voltage (v lcd ). 32 2 3 4 32 32 32 v cc v 2 v 3 gnd v 1 com1 seg1 to seg32 v cc v 2 v 3 gnd v 1 com1 com2 seg1 to seg32 v cc v 2 v 3 gnd v 1 com1 to com3 seg1 to seg32 v cc v 2 v 3 gnd v 1 com1 to com4 seg1 to seg32 v cc v lcd v cc v lcd v cc v lcd v cc v lcd r r r v (v ) cc 1 v 2 v 3 gnd r r r v (v ) cc 1 v 2 v 3 gnd c c c c = 0.1 to 0.3 f 4-digit lcd with sign . 8-digit lcd 10-digit lcd with sign 16-digit lcd . . . static drive 1/2 duty cycle, 1/2 bias drive 1/3 duty cycle, 1/3 bias drive 1/4 duty cycle, 1/3 bias drive v 3 v 3 gnd cc lcd figure 38 lcd connection examples
HD404618 series 62 dtmf generation circuit the mcu has a dual-tone multifrequency (dtmf) generation circuit. the dtmf signal consists of two sine waves to access the switching system. figure 39 shows the dtmf keypad and frequencies. pressing a key generates a tone corresponding to its frequency. figure 40 shows a block diagram of the dtmf circuit. the mcu uses an oscillation frequency reduced to 400 khz, an eighth of the conventionally used frequency, for low-power consumption. this, however, causes a potential frequency deviation. the mcu provides transformed programmable dividers in addition to sine wave counters and a control register to reduce frequency deviation. the dtmf generation circuit is controlled by the following three registers. 1 4 7 * 2 5 8 0 3 6 9 # a b c d r1 (697 hz) r2 (770 hz) r3 (852 hz) r4 (941 hz) c1 (1209 hz) c2 (1336 hz) c3 (1477 hz) c4 (1633 hz) figure 39 dtmf keypad and frequencies
HD404618 series 63 400 khz (selected at tgsp reset) 800 khz tgsp flag toner vt ref tonec sine wave counter d/a transformed programmable divider transformed programmable divider sine wave counter d/a dtmf register feedback feedback figure 40 dtmf circuit block diagram tone generator mode register (tgm: $010): four-bit write-only register which controls output frequencies (see table 30). it is cleared to $0 by mcu reset. table 30 tone generator mode register tgm bit 3 bit 2 bit 1 bit 0 output frequencies option (toner output is not affected) 00 f r1 (697 hz) output through toner pin 01 f r2 (770 hz) 10 f r3 (852 hz) 11 f r4 (941 hz) 0 0 option (tonec output is not affected) f c1 (1,209 hz) output through tonec pin 01 f c2 (1,336 hz) 10 f c3 (1,477 hz) 11 f c4 (1,633 hz) tone generator control register (tgc: $011): three-bit write-only register which controls the start and stop of dtmf signal output (see table 31). it is cleared to $0 by mcu reset.
HD404618 series 64 table 31 tone generator control register tgc bit 1 dtmf enable bit 0 dtmf disabled 1 dtmf enabled tgc bit 2 toner output control (row) 0 stopped 1 toner output (active) tgc bit 3 tonec output control (column) 0 stopped 1 tonec output (active) tone generator speed flag (tgsp: $020,bit 2): one-bit register which can be set and reset by the sem/rem and semd/remd instructions. the dtmf generation circuit generates output frequencies with a 400-khz clock (table 30). with an 800-khz clock, the dtmf generation circuit generates these same frequencies by pulling the tgsp flag high. dtmf output: the sine waves of the row-group and column-group are individually converted from digital to analog in the d/a conversion circuit, which provides high-precision ladder resistance. the dtmf output pins, toner and tonec, transmit the sine waves of the row-group and column-group, respectively. figure 41 shows thetone output equivalent circuit. figure 42 shows the output waveform. one cycle of this wave consists of 32 time slots, making the output waveform stable with little distortion. table 32 lists the frequency deviation of the mcu from standard dtmf signals. vt ref gnd switch control toner tonec figure 41 tone output equivalent circuit
HD404618 series 65 vt ref gnd time slots 12345678910 12 11 13 14 15 16 18 19 17 20 21 22 23 24 25 26 27 28 29 30 31 32 figure 42 waveform of tone output table 32 frequency deviation of the mcu from standard dtmf signals standard dtmf (hz) mcu (hz) deviation from standard (%) r1 697 694.44 ?.37 r2 770 769.23 ?.10 r3 852 851.06 ?.11 r4 941 938.97 ?.22 c1 1,209 1,212.12 0.26 c2 1,336 1,333.33 ?.20 c3 1,477 1,481.48 0.30 c4 1,633 1,639.34 0.39 note: this frequency deviation value does not include the frequency deviation due to the oscillator element. also note that in this case the ratio of the high level and low level widths in the oscillator waveform due to the oscillator element will be 50% : 50%.
HD404618 series 66 programmable rom the hd4074618 is a ztat ? microcomputer with built-in prom that can be programmed in prom mode. prom mode pin description pin number mcu mode prom mode pin number mcu mode prom mode fp-80b fp-80a, tfp-80 pin name i/o pin name i/o fp-80b fp-80a, tfp-80 pin name i/o pin name i/o 179 d 2 i/o o 2 i/o 28 26 r2 3 i/o a 12 i 280 d 3 i/o o 3 i/o 29 27 r3 0 i/o a 13 i 31 d 4 i/o o 4 i/o 30 28 r3 1 /timo i/o a 14 i 42 d 5 i/o o 5 i/o 31 29 r3 2 / int 0 i/o ce i 53 d 6 i/o o 6 i/o 32 30 r3 3 / int 1 i/o oe i 64 d 7 i/o o 7 i/o 33 31 seg1 o 75 d 8 i/o 34 32 seg2 o 86 d 9 i/o 35 33 seg3 o 97 d 10 iv pp 36 34 seg4 o 10 8 d 11 /vc ref ia 9 i 37 35 seg5 o 11 9 d 12 /comp 0 i m0 i 38 36 seg6 o 12 10 d 13 /comp 1 i m1 i 39 37 seg7 o 13 11 test i test i 40 38 seg8 o 14 12 x1 i gnd 41 39 seg9 o 15 13 x2 o 42 40 seg10 o 16 14 gnd gnd 43 41 seg11 o 17 15 r0 0 / sck i/o a 1 i 44 42 seg12 o 18 16 r0 1 /si i/o a 2 i 45 43 seg13 o 19 17 r0 2 /so i/o a 3 i 46 44 seg14 o 20 18 r0 3 i/o a 4 i 47 45 seg15 o 21 19 r1 0 i/o a 5 i 48 46 seg16 o 22 20 r1 1 i/o a 6 i 49 47 seg17 o 23 21 r1 2 i/o a 7 i 50 48 seg18 o 24 22 r1 3 i/o a 8 i 51 49 seg19 o 25 23 r2 0 i/o a 0 i 52 50 seg20 o 26 24 r2 1 i/o a 10 i 53 51 seg21 o 27 25 r2 2 i/o a 11 i 54 52 seg22 o
HD404618 series 67 pin number mcu mode prom mode pin number mcu mode prom mode fp-80b fp-80a, tfp-80 pin name i/o pin name i/o fp-80b fp-80a, tfp-80 pin name i/o pin name i/o 55 53 seg23 o 68 66 com4 o 56 54 seg24 o 69 67 v 1 57 55 seg25 o 70 68 v 2 58 56 seg26 o 71 69 v 3 v cc 59 57 seg27 o 72 70 tonec o 60 58 seg28 o 73 71 toner o 61 59 seg29 o 74 72 vt ref v cc 62 60 seg30 o 75 73 v cc v cc 63 61 seg31 o 76 74 osc 1 iv cc 64 62 seg32 o 77 75 osc 2 o 65 63 com1 o 78 76 reset i reset i 66 64 com2 o 79 77 d 0 i/o o 0 i/o 67 65 com3 o 80 78 d 1 i/o o 1 i/o
HD404618 series 68 programming the built-in prom the mcu? built-in prom is programmed in prom mode which is set by pulling test , m 0 , and m 1 low, and reset high, as shown in figure 43. in prom mode, the mcu does not operate, but it can be programmed in the same way as any other commercial 27256 eprom using a standard prom programmer and a 80-to-28-pin socket adaptor. recommended prom programmers and socket adapters are listed in table 34. since an hmcs400-series instruction is ten bits long, the hmcs400-series mcu has a built-in conversion circuit to enable use of a general-purpose prom programmer. this circuit splits each instruction into a lower 5 bits and an upper 5 bits that are read from or written to consecutive addresse. this means that if, for example, 8 kwords of built-in prom are to be programmed by a general-purpose prom programmer, a 16-kbyte address space ($0000?3fff) must be specified. programming and verification: the built-in prom of the mcu can be programmed at high-speed programming sequence without risk of voltage stress or damage to data reliability. for details of prom programming, refer to the notes on prom programming section. warnings 1. always specify addresses $0000 to $3fff when programming with a prom programmer. if address $4000 or higher is accessed, the prom may not be programmed or verified correctly. set all data in unused addresses to $ff. note that the plastic-package version cannot be erased and reprogrammed. 2. make sure that the prom programmer, socket adapter, and lsi are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the lsi. before starting programming, make sure that the lsi is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. prom programmers have two voltages (v pp ): 12.5 v and 21 v. remember that ztat ? devices require a v pp of 12.5 v?he 21-v setting will damage them. 12.5 v is the intel? 27256 setting. table 33 prom mode selection pin mode ce oe v pp o 0 ? 7 programming low high v pp data input verification high low v pp data output programming inhibition high high v pp high impedance
HD404618 series 69 table 34 recommended prom programmers and socket adapters prom programmer socket adapter manufacturer model name manufacturer model name package data i/o corp. 121b 29b hitachi hs460esf01h fp-80b hs460esh01h fp-80a hs461est01h tfp-80 aval corp. pkw-1000 hitachi hs460esf01h fp-80b hs460esh01h fp-80a hs461est01h tfp-80 o ? 07 a ? 014 address a to a 014 data o to o 07 oe ce oe ce gnd d /v 10 pp v cc v cc v pp reset test m m v cc osc 1 vt ref v 3 x1 0 1 v cc figure 43 connections for prom mode
HD404618 series 70 addressing modes ram addressing modes the mcu has three ram addressing modes, as shown in figure 44 and described below. register indirect addressing mode: the contents of the w, x, and y registers (10 bits in total) are used as a ram address. direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode: the memory registers (mr), consisting of 16 digits from $040 to $04f, are accessed with the lamr and xmra instructions. ap 9 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 w 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 w register x register y register ram address register indirect addressing ap 9 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 ram address direct addressing d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd word of instruction opcode 1st word of instruction ap 9 ap 8 ap 7 ap ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 ram address memory register addressing m 3 m 2 m 1 m 0 opcode instruction 000100 6 figure 44 ram addressing modes
HD404618 series 71 rom addressing modes and the p instruction the mcu has four rom addressing modes, as shown in figure 45 and described below. direct addressing mode: a program can branch to any address in the rom memory space by executing the jmpl, brl, or call instruction. each of these instructions replaces the 14 program counter bits (pc 13 ?c 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 32 pages of rom with 256 words per page. a program can branch to any address in the current page by executing the br instruction. this instruction replaces the eight low-order bits of the program counter (pc 7 ?c 0 ) with eight-bit immediate data. if the br instruction is on a page boundary (address 256n + 255), executing that instruction transfers the pc contents to the next physical page, as shown in figure 46. this means that the execution of the br instruction on a page boundary will make the program branch to the next page. note that the hmcs400-series cross macro-assembler has an automatic paging feature for rom pages. zero-page addressing mode: a program can branch to the zero-page subroutine area located at $000 $003f by executing the cal instruction. when the cal instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (pc 5 ?c 0 ), and 0s are placed in the eight high- order bits (pc 13 ?c 6 ). table data addressing mode: a program can branch to an address determined by the contents of four- bit immediate data, the accumulator, and the b register by executing the tbr instruction. p instruction: rom data addressed in table data addressing mode can be referenced with the p instruction as shown in figure 47. if bit 8 of the rom data is 1, eight bits of rom data are written to the accumulator and the b register. if bit 9 is 1, eight bits of rom data are written to the r1 and r2 port output registers. if both bits 8 and 9 are 1, rom data is written to the accumulator and the b register, and also to the r1 and r2 port output registers at the same time. the p instruction has no effect on the program counter.
HD404618 series 72 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd word of instruction opcode 1st word of instruction p 0 p 1 p 2 p 3 [jmpl] [brl] [call] pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc pc 10 11 12 13 program counter direct addressing zero page addressing a 5 a 4 a 3 a 2 a 1 a 0 instruction [cal] opcode pc 98 pc 76 pc 54 pc 3 pc 1 pc 0 pc pc 10 11 12 13 program counter 00 00 0 0 0 0 pc pc pc pc pc pc 2 b 1 b 0 a 3 a 2 a 1 a 0 accumulator program counter table data addressing pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc 10 11 12 13 b 2 b 3 b register p 3 p 0 [tbr] instruction opcode 0 0 p 2 p 1 pc opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 instruction pc 90 pc pc pc 11 12 13 program counter current page addressing [br] pc 10 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc pc 8 pc figure 45 rom addressing modes
HD404618 series 73 br aaa aaa nop 256 (n ?1) + 255 256 n br aaa br bbb 256 n + 254 256 n + 255 256 (n + 1) bbb nop figure 46 page boundary between br instruction and branch destination
HD404618 series 74 b 1 b 0 a 3 a 2 a 1 a 0 accumulator referred rom address address specification ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 ra ra ra 10 11 12 13 b 2 b 3 b register 0 0 p 3 p 0 [p] instruction opcode p 2 p 1 ra ro 9 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 bbbb aa a a 3210 3210 if ro = 1 8 accumulator, b register rom data pattern output ro 9 rom data r2 32103 210 if ro = 1 9 output registers r1, r2 r2 r2 r2 r1 r1 r1 r1 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 figure 47 p instruction
HD404618 series 75 absolute maximum ratings item symbol value unit notes supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to (v cc + 0.3) v total permissible input current ? i o 100 ma 2 total permissible output current ? i o 50 ma 3 maximum input current i o 4 ma 4, 5 30 ma 4, 6 maximum output current ? o 4 ma 7, 8 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. d 10 (v pp ) of the hd4074618. 2. total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to gnd. 3. total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 4. the maximum input current is the maximum current flowing from any i/o pin to ground. 5. applies to r0?3 6. applies to d 0 ? 9 7. the maximum output current is the maximum current flowing from v cc to any i/o pin. 8. applies to d 0 ? 9 , r0?3
HD404618 series 76 electrical characteristics (please inquire about the characteristics of hd404612, hd404614, hd404616, and HD404618 at v cc = 2.2 v) dc characteristics (hd404612, hd404614, hd404616, HD404618: v cc = 2.7 v to 6.0 v; hd4074618: v cc = 3.0 v to 5.5 v, gnd = 0.0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih reset, sck , int 0 , int 1 0.9v cc v cc + 0.3 v osc 1 v cc ?0.3 v cc + 0.3 v external clock operation si 0.9v cc v cc + 0.3 v input low voltage v il reset, sck , int 0 , int 1 ?.3 0.1v cc v osc 1 ?.3 0.3 v external clock operation si ?.3 0.1v cc v output high voltage v oh sck , timo, so v cc ?1.0 v i oh = 0.5 ma output low voltage v ol sck , timo, so 0.4 v i ol = 0.4 ma i/o leakage current |i il | reset, sck , int 0 , int 1 , si, so, timo, osc 1 1 m av in = 0 to v cc 1 stop mode retaining voltage v stop v cc 2 v no 32-khz oscillator 7 current dissipation in i cc1 v cc 400 1000 m av cc = 3 v f osc = 400 khz 2 active mode i cc2 v cc 500 1500 m av cc = 3 v dtmf: active f osc = 400 khz 3 i cc3 v cc 1 2 ma v cc = 3 v f osc = 400 khz d 12 , d 13 analog input mode 4 current dissipation in standby mode i sby v cc 200 500 m av cc = 3 v lcd on f osc = 400 khz 5 current dissipation in stop mode i stop v cc 110 m av cc = 3 v no 32-khz oscillator
HD404618 series 77 item symbol pin(s) min typ max unit test condition notes current dissipation in subactive mode i sub v cc 50 100 m av cc = 3 v lcd on 35 70 m a6 current dissipation in watch mode (1) i wtc1 v cc 515 m av cc = 3 v lcd off current dissipation in watch mode (2) i wtc2 v cc 15 35 m av cc = 3 v lcd on comparator input reference voltage scope vc ref vc ref 0v cc ?1.2 v notes: 1. output buffer current is excluded. 2. i cc is the source current when no i/o current is flowing while the mcu is in reset state. test conditions: mcu: reset pins: reset, test at v cc 3. i sby is the source current when no i/o current is flowing while the mcu timer is in operation. test conditions: d 12 , d 13 in digital input mode dtmf in operation (excludes current flowing from vt ref to gnd) 4. pins d 12 and d 13 are in analog input mode and i/o current is not flowing. test conditions: vc ref /d 11 , comp0/d 12 , comp1/d 13 at gnd dtmf stopped 5. timer is in operation and i/o current is not flowing. test conditions: mcu: i/o in reset state serial interface stopped d 12 , d 13 in digital input mode dtmf stopped stanby mode pins : reset at gnd test at v cc 6. applies only to hd404612, hd404614, hd404616, and HD404618. 7. ram data retention.
HD404618 series 78 i/o characteristics for standard pins (hd404612, hd404614, hd404616, HD404618: v cc = 2.7 v to 6.0 v; hd4074618: v cc = 3.0 v to 5.5 v, gnd = 0.0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max test conditions unit notes input high voltage v ih d 10 ? 13 , r0?r3 0.7v cc ? cc + 0.3 v input low voltage v il d 10 ? 13 , r0?3 ?.3 0.3v cc v output high voltage v oh r0?3 v cc ?1.0 ? oh = 0.5 ma v pull-up mos current ? pu r0?3 5 40 90 v cc = 3 v, v in = 0 v m a output low voltage v ol r0?3 0.4 i ol = 0.4 ma v i/o leakage current |i il |d 11 to d 13 , r0 to r3 1 hd404612, hd404614 hd404616, HD404618: v in = 0 v to v cc m a1 d 10 20 hd4074618: v in = 0 v to v cc m a2 input high voltage v iha d 12 , d 13 (analog compare mode) vc ref + 0.1 v input low voltage v ila d 12 , d 13 (analog compare mode) vc ref ?0.1 v note: 1. output buffer current is excluded. 2. the max value for the HD404618, hd404616, hd404614, and hd404612 is 1 m a.
HD404618 series 79 i/o characteristics for high-current pins (hd404612, hd404614, hd404616, HD404618: v cc = 2.7 v to 6.0 v; hd4074618: v cc = 3.0 v to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max test conditions unit notes input high voltage v ih d 0 ? 9 0.7v cc ? cc + 0.3 v input low voltage v il d 0 ? 9 ?.3 0.3v cc v output high voltage v oh d 0 ? 9 v cc ?1.0 i oh = 0.5 ma v pull-up mos current ? pu d 0 ? 9 54090v cc = 3 v, v in = 0 v m a output low voltage v ol d 0 ? 9 2.0 i ol = 15 ma v cc = 4.5 v to 6 v v 0.4 i ol = 0.4 ma v i/o leakage current |i il |d 0 ? 9 1 v in = 0 to v cc m a1 note: 1. output buffer current is excluded. lcd circuit characteristics (hd404612, hd404614, hd404616, HD404618: v cc = 2.7 v to 6.0 v; hd4074618: v cc = 3.0 v to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max test condition unit notes segment driver voltage drop v ds seg1 seg32 0.6 i d = 3 m av1 common driver voltage drop v dc com1 com4 0.3 i d = 3 m av1 lcd power supply division resistor r well 100 300 900 between v 1 and gnd k w lcd voltage v lcd v 1 2.7 v cc hd404612, hd404614, hd404616, HD404618 v2 3.0 v cc hd4074618 v 2 notes: 1. v ds and v dc are the voltage drops from power supply pins v 1 , v 2 , and v 3 , and gnd to each segment pin and each common pin. 2. when v lcd is supplied from an external source, the following relations must be retained: v cc 3 v 1 3 v 2 3 v 3 3 gnd
HD404618 series 80 dtmf characteristics (hd404612, hd404614, hd404616, HD404618: v cc = 2.7 v to 6.0 v; hd4074618: v cc = 3.0 v to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max test conditions unit notes tone output voltage (1) v or toner 500 660 vt ref ?gnd = 2.0 v, r l = 100 k w mv rms 1 tone output voltage (2) v oc tonec 520 690 vt ref ?gnd = 2.0 v, r l = 100 k w mv rms 1 tone output distortion %dis 3 7 short circuit between toner and tonec, r l = 100 k w %2 tone output ratio db cr 2.5 short circuit between toner and tonec, r l = 100 k w db 2 notes: 1. see figure 48. 2. see figure 49.
HD404618 series 81 ac characteristics (hd404612, hd404614, hd404616, HD404618: v cc = 2.7 v to 6.0 v; hd4074618: v cc = 3.0 v to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max test condition unit notes clock oscillation frequency f osc osc 1 , osc 2 400 1/4 division khz 800 khz x1, x2 32.768 khz instruction cycle time t cyc ?0 f osc / f cp = 400 khz m s ? f osc / f cp = 800 khz m s oscillator stabilization time t rc osc 1 , osc 2 7.5 f osc = 400 khz ms 1 7.5 f osc = 800 khz ms 1 x1, x2 3 t a = ?0 to +60 cs 2 external clock frequency f cp osc 1 400 khz 800 khz external clock high width t cph osc 1 1100 f cp = 400 khz ns 3 550 f cp = 800 khz ns 3 external clock low width t cpl osc 1 1100 f cp = 400 khz ns 3 550 f cp = 800 khz ns 3 external clock rise time t cpr osc 1 150 f cp = 400 khz ns 3 75 f cp = 800 khz ns 3 external clock fall time t cpf osc 1 150 f cp = 400 khz ns 3 75 f cp = 800 khz ns 3 int 0 high width t ih int 0 2 t cyc / t subcyc 4, 6 int 0 low width t il int 0 2 t cyc / t subcyc 4, 6 int 1 high width t ih int 1 2 t cyc 4
HD404618 series 82 item symbol pin(s) min typ max test condition unit notes int 1 low width t il int 1 2 t cyc 4 reset high width t rsth reset 2 t cyc 5 input capacitance c in d 10 90 hd4074618: f = 1 mhz, v in = 0 v pf 8 all pins except d 10 15 f = 1 mhz, v in = 0 v pf reset fall time t rstf 20 ms 5 analog comparator stabilization time t cstb d 12 , d 13 (analog input mode) 2 t cyc 7 notes: 1. the oscillation stabilization time is the period required for the oscillator to stabilize after v cc reaches 2.7 v (3.0 v for hd4074618) at power-on or after reset input goes high after stop mode is cancelled. at power-on or when stop mode is cancelled, reset must remain high for at least t rc to ensure the oscillation stabilization time. since t rc depends on the ceramic oscillator? circuit constant and stray capacitance, contact the manufacturer when designing a reset circuit. 2. the oscillation stabilization time is the period required for the oscillator to stabilize after v cc reaches 2.7 v (3.0 v for hd4074618) at power-on. the oscillation stabilization time (t rc ) must be ensured. if using a crystal oscillator, contact the manufacturer to determine what oscillation stabilization time is required, since it depends on the circuit constants and stray capacitances. 3. see figure 50. 4. see figure 51. the unit t cyc applies when the mcu is in standby mode or active mode. 5. see figure 52. 6. the unit t subcyc applies when the mcu is in watch mode or subactive mode. t subcyc = 244.14 m s (32.768-khz crystal oscillator) 7. the analog comparator stabilization time is the period required for the oscillator to stabilize and for correct data to be read after d 12 /d 13 is input to enter analog input mode. 8. the max value for the HD404618, hd404616, hd404614, and hd404612 is 15pf.
HD404618 series 83 serial interface timing characteristics (hd404612, hd404614, hd404616, HD404618: v cc = 2.7 v to 6.0 v; hd4074618: v cc = 3.0 v to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) during transmit clock output item symbol pin(s) min typ max test condition unit notes transmit clock cycle time t scyc sck 1 load shown in figure 54 t cyc /t subcyc 1, 3 transmit clock high width t sckh sck 0.5 load shown in figure 54 t scyc 1 transmit clock low width t sckl sck 0.5 load shown in figure 54 t scyc 1 transmit clock rise time t sckr sck 200 load shown in figure 54 ns 1 transmit clock fall time t sckf sck 200 load shown in figure 54 ns 1 serial output data delay time t dso so 500 load shown in figure 54 ns 1 serial input data setup time t ssi si 300 ns 1 serial input data hold time t hsi si 300 ns 1
HD404618 series 84 during transmit clock input item symbol pin(s) min typ max test condition unit notes transmit clock cycle time t scyc sck 1 t cyc /t subcyc 1, 3 transmit clock high width t sckh sck 0.5 t scyc 1 transmit clock low width t sckl sck 0.5 t scyc 1 transmit clock rise time t sckr sck 200 ns 1 transmit clock fall time t sckf sck 200 ns 1 serial output data delay time t dso so 500 load shown in figure 54 ns 1 serial input data setup time t ssi si 300 ns 1 serial input data hold time t hsi si 300 ns 1 transmit clock completion detect time t sckhd sck 1 t cyc /t subcyc 1, 2, 3 notes: 1. see figure 53. 2. the transmit clock completion detect time is the high level period after eight transmit clock pulses have been input. the serial interrupt request flag is not set if the next transmit clock is input before the transmit clock completion detect time has passed. 3. the unit t subcyc applies when the mcu is in subactive mode. t subcyc = 244.14 m s (32.768-khz crystal oscillator) tonec toner r = 100 k w l r = 100 k w l figure 48 tone output load circuit
HD404618 series 85 tonec toner r = 100 k l w figure 49 distortion and db cr load circuit t cpr t cpf v ?0.3 v cc 0.3 v osc 1 t cph t cpl 1/f cp figure 50 oscillator timing 0.9v cc 0.1v cc int , int 01 t ih t il figure 51 interrupt timing reset t rstf t rsth 0.9v 0.1v cc cc figure 52 reset timing 0.9v cc 0.1v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr t sckh 0.4 v v ?0.5 v cc v ?1.0 v (0.9v ) cc 0.4 v (0.1v ) sck so si t sckhd after 8 transmit clock pulses are input v ?1.0 v and 0.4 v are the threshold voltages for transmit clock output. 0.9v and 0.1v are threshold voltages for transmit clock input. cc cc cc cc cc * * * note: figure 53 serial interface timing
HD404618 series 86 test point 30 pf c 12 k w r v cc r = 2.6 k l w 1s2074 h or equivalent figure 54 timing load circuit
HD404618 series 87 notes on rom out please pay attention to the following items regarding rom out. on rom out, fill the rom area indicated below with 1s to create the same data size as a 8-kword version (HD404618). an 8-kword data size is required to change rom data to mask manufac turing data since the program used is for a 8-kword version. this limitation applies when using an eprom or a data base. vector address zero-page subroutine (64 words) pattern & program (2,048 words) not used vector address zero-page subroutine (64 words) pattern & program (4,096 words) not used rom 2-kword version: hd404612 address $0800?1fff $0000 $000f $0010 $003f $0040 $07ff $0800 $1fff $0000 $000f $0010 $003f $0040 $0fff $1000 $1fff fill this area with 1s rom 4-kword version: hd404614 address $1000?1fff vector address zero-page subroutine (64 words) pattern & program (6,144 words) not used $0000 $000f $0010 $003f $0040 $17ff $1800 $1fff rom 6-kword version: hd404616 address $1800?1fff
HD404618 series 88 hd404612, hd404614, hd404616, HD404618 option list please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). 5. rom code media 7. stop mode used not used 8. package fp-80a fp-80b tfp-80 eprom: the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 6. system oscillator (osc1 and osc2) ceramic oscillator external clock f = f = mhz mhz date of order customer department rom code name lsi number (to be filled in by hitachi) / / 1. rom size please check off the appropriate applications and enter the necessary information. hd404612 hd404614 hd404616 HD404618 2-kword 4-kword 6-kword 8-kword 2. optional functions note: * options marked with an asterisk require a subsystem crystal oscillator * * with 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, without time-base
HD404618 series 89 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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